1. Field of the Invention
The present invention generally relates to Programmable Logic Devices (PLDs), and more particularly, to PLDs with logic modules having more registered outputs than combinational outputs; and/or a combinational output that can drive more than one output register.
2. Description of Related Art
A Programmable Logic Device (PLD) is a semiconductor integrated circuit that contains fixed logic circuitry that can be programmed to perform a host of logic functions. In the semiconductor industry, PLDs are becoming increasingly popular for a number of reasons. Due to the advances of chip manufacturing technology, application specific integrated circuits (ASICs) designs have become incredibly complex. This complexity not only adds to design costs, but also the duration of time needed to develop an application specific design. To compound this problem, product life cycles are shrinking rapidly. As a result, it is often not feasible for original equipment manufacturers (OEMs) to design and use ASICs. OEMs are therefore relying more and more on PLDs. The same advances in fabrication technology have also resulted in PLDs with improved density and speed performance. Sophisticated programming software enables complex logic functions to be rapidly developed for PLDs. Furthermore, logic designs generally can also be easily migrated from one generation of PLDs to the next, further reducing product development times. The closing of the price-performance gap with ASICs, and reduced product development times, makes the use of PLDs compelling for many OEMs.
The architecture of most PLDs defines a two-dimensional array of logic blocks. Row and column inter-logic block lines, typically of varying length and speed, provide signal and clock interconnects between the blocks of logic in the array. The blocks of logic are often referred to by various names, for example as Logic Array Blocks or LABs by the Altera Corporation, assignee of the present application, or Complex Logic Blocks (CLBs), as used by Xilinx Corporation. In the Altera architectures, the LABs are further broken into a plurality of individual logic elements, typically referred to as either Logic Elements (LEs) or Adaptive Logic Modules (ALMs). With the Xilinx architecture, the CLBs also include a group of logic elements called Logic Cells or (LCs). The LEs, LCs, or ALMS each typically include such elements as look up tables (LUTs), registers for generating registered outputs, adders and other circuitry to implement various logic and arithmetic functions. For the sake of simplicity, any module of logic, regardless of referring to an LE, an ALM, or a LC, will hereafter be generically referred to as a “logic module”. Similarly, any block of logic, whether a LAB or a CLB, is hereafter generically referred to as a “logic array block”. In no way should the terms “logic module” or “logic array block” be construed as limiting the present invention to a particular PLD architecture and is intended to cover any PLD architecture that uses any type of module of logic grouped into a logic array block, including but not limited to the PLDs offered by Altera and Xilinx.
Historically, logic modules in PLDs have conventionally included only one register per combinational output from a combinational logic generator, such as a Look Up Table or LUT), in the module. These logic modules have therefore been conventionally been limited to: (i) generating a single non-registered combinational function; (ii) generating a single a registered combinational function; (iii) generating a single non-registered combinational function while the register was used for an unrelated flip flop operation; or (iv) use of the register only as a flip flop. Thus, with conventional logic modules, the output register could select from either the combinational output from the LUT, or some other input to the logic module, while driving either a global interconnect or an input to the LUT though a register feedback connection.
The conventional logic module as described above has become inadequate for a number of practical reasons. In many current user logic designs for PLDs, a large number of flip flops are often required for reasons such as pipelining, the use of shift registers to store data, etc. Furthermore, PLDs that use larger lookup tables such as 6 input functions exhibit a reduced ratio of flip flops to combinational logic because of the increased logic functionality of the 6 LUT compared to previous 4 LUT logic blocks. With designs that require many flip flops, it is possible to use a given logic module to implement both a combinational logic function in the LUT and separately use the output register for some other flip flop operation. This implementation, however, is typically undesirable. It often causes placement constraints, which negatively affect the speed of the design. As a result, the logic module is typically used to implement either a combinational function or a flip flop function, but not both functions. Consequently, efficiency is detrimentally effected as more logic modules may be needed than ordinarily required to implement the number of combinational and flip flop functions specified for a given logic design. Even when a user's design defines a smaller number of flip flops as compared to combinational functions, the actual implementation may require the use of a larger number of logic modules than otherwise required since some of the modules may be dedicated only for flip flop functions.
A PLD that has more flip flops per logic module by providing (i) more registered outputs than combinational outputs; and/or (ii) a combinational output that can drive more than one output register, is therefore needed.